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ltc4266 4266fa n high power pse switches/routers n high power pse midspans applic a tions fe a tures description quad ieee 802.3at power over ethernet controller the ltc ? 4266 is a quad pse controller designed for use in ieee 802.3 type 1 and type 2 (high power) compliant power over ethernet systems. external power mosfets enhance system reliability and minimize channel resis - tance, cutting power dissipation and eliminating the need for heatsinks even at type 2 power levels. external power components also allow use at very high power levels while remaining otherwise compatible with the ieee standard. 80v-rated port pins provide robust protection against external faults. the ltc4266 includes advanced power management features, including current and voltage readback and programmable i cut and i lim thresholds. available c librar- ies simplify power-management software development; an optional auto mode provides fully ieee-compliant standalone operation with no software required. proprietary 4-point pd detection circuitry minimizes false pd detec - tion while supporting legacy phone operation. midspan operation is supported with built-in 2-event classification and backoff timing. host communication is via a 1mhz i 2 c serial interface. the ltc4266 is available in a 5mm 7mm qfn package that significantly reduces board space compared with competing solutions. a legacy-compatible 36-pin ssop package is also available. n four independent pse channels n compliant with ieee 802.3at type 1 and 2 n 0.34 total channel resistance 130mw/port at 600ma n advanced power management 8-bit programmable current limit (i lim ) 7-bit programmable overload currents (i cut ) fast shutdown of preselected ports 14.5-bit port current/voltage monitoring 2-event classification n very high reliability 4-point pd detection: 2-point forced voltage 2-point forced current n high capacitance legacy device detection n ltc4259a-1 and ltc4258 pin and sw compatible n 1mhz i 2 c compatible serial control interface n midspan backoff timer n supports proprietary power levels above 25w n available in 38-pin 5mm 7mm qfn and 36-pin ssop packages t ypic a l applic a tion complete 4-port ethernet high power source l, lt, ltc, ltm, linear technology and the linear logo are registered trademarks and thinsot is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 4266 ta01 scl sdain sdaout ad0 ad1 ad2 ad3 a gnd v ee sense1 ?50v 1f smaj58a gate1 out1 out2 out3 sense2 gate2 sense3 gate3 sense4 gate4 out4 port1 ?50v 0.22f 100v s4 s1b s4 s1b s4 port2 port3 port4 d gnd v dd int shdn1 shdn2 auto msd reset shdn3 shdn4 mid 0.1f 3.3v ltc4266
ltc4266 4266fa absolute m a xi m u m ra tings p in c on f igur a tion o r d er i n f or ma tion lead free finish tape and reel part marking* package description temperature range ltc4266cgw#pbf ltc4266cgw#trpbf ltc4266 36-lead plastic wide ssop 0c to 70c ltc4266igw#pbf ltc4266igw#trpbf ltc4266 36-lead plastic wide ssop C40c to 85c ltc4266cuhf#pbf ltc4266cuhf#trpbf 4266 38-lead (5mm 7mm) plastic qfn 0c to 70c ltc4266iuhf#pbf ltc4266iuhf#trpbf 4266 38-lead (5mm 7mm) plastic qfn C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view gw36 package 36-lead plastic wide ssop t jmax = 125c, q ja = 80c/w 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 reset mid int scl sdaout sdain ad3 ad2 ad1 ad0 nc nc nc nc d gnd v dd shdn1 shdn2 msd auto out1 gate1 sense1 out2 gate2 sense2 v ee out3 gate3 sense3 out4 gate4 sense4 a gnd shdn4 shdn3 13 14 15 16 top view 39 uhf package 38-lead (5mm s 7mm) plastic qfn exposed pad is v ee (pin 39) must be soldered to pcb t jmax = 125c, q ja = 34c/w 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1sdaout nc sdain ad3 ad2 ad1 ad0 dnc nc d gnd nc nc gate1 sense1 out2 gate2 sense2 v ee v ee out3 gate3 sense3 out4 gate4 scl int mid reset msd auto out1 v dd shdn1 shdn2 shdn3 shdn4 a gnd sense4 23 22 21 20 9 10 11 12 supply voltages (note 1) a gnd C v ee ............................................. C0.3v to 80v d gnd C v ee ................................................. C0.3v to 80v v dd C dgnd .............................................. C0.3v to 5.5v digital pins s c l, sdain, sdaout, int , shdn n, msd , adn, reset , auto, mid........... dgnd C0.3v to v dd + 0.3v analog pins g a ten, sensen, outn .......... v ee C0.3v to v ee + 80v operating temperature range ltc4266c ................................................ 0 c to 70c ltc4266i .............................................C 4 0c to 85c junction temperature (note 2) ............................. 125c s t orage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec) ................... 3 0 0c
ltc4266 4266fa e lectric a l c h a r a cteristics symbol parameter conditions min typ max units C48v supply voltage a gnd C v ee for ieee type 1 complaint output for ieee type 2 complaint output l l 45 51 57 57 v v under voltage lock-out level l 20 25 30 v v dd v dd supply voltage v dd C d gnd l 3.0 3.3 4.3 v undervoltage lock-out l 2.2 v allowable digital ground offset d gnd C v ee l 25 57 v i ee v ee supply current (a gnd C v ee ) = 55v l C2.4 C5 ma i dd v dd supply current (v dd C d gnd ) = 3.3v l 1.1 3 ma detection detection current C force current first point, a gnd C v outn = 9v second point, a gnd C v outn = 3.5v l l 220 140 240 160 260 180 a a detection voltage C force voltage a gnd C v outn , 5a i outn 500a first point second point l l 7 3 8 4 9 5 v v detection current compliance a gnd C v outn = 0v l 0.8 0.9 ma v oc detection voltage compliance a gnd C v outn , open port l 10.4 12 v detection voltage slew rate a gnd C v outn , c port = 0.15f l 0.01 v/s min. valid signature resistance l 15.5 17 18.5 k max. valid signature resistance l 27.5 29.7 32 k classification v class classification voltage a gnd C v outn , 0ma i class 50ma l 16.0 20.5 v classification current compliance v outn = a gnd l 53 61 67 ma classification threshold current class 0 C 1 class 1 C 2 class 2 C 3 class 3 C 4 class 4 C overcurrent l l l l l 5.5 13.5 21.5 31.5 45.2 6.5 14.5 23 33 48 7.5 15.5 24.5 34.9 50.8 ma ma ma ma ma v mark classification mark state voltage a gnd C v outn , 0.1ma i class 10ma l 7.5 9 10 v mark state current compliance v outn = a gnd l 53 61 67 ma gate driver gate pin pull-down current port off, v gaten = v ee + 5v port off, v gaten = v ee + 1v l l 0.4 0.08 0.12 ma ma ga te pin fast pull-down current v gaten = v ee + 5v 30 ma gate pin on voltage v gaten C v ee , i gaten = 1a l 8 14 v output voltage sense v pg power good threshold voltage v outn C v ee l 2 2.4 2.8 v out pin pull-up resistance to a gnd 0v (a gnd C v outn ) 5v l 300 500 700 k the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a gnd C v ee = 54v, a gnd = d gnd , and v dd C d gnd = 3.3v unless otherwise noted. (notes 3, 4)
ltc4266 4266fa symbol parameter conditions min typ max units current sense v cut overcurrent sense voltage v sensen C v ee , icut12 = icut34 = hpen = 00h hpen = 0fh, cutn[5:0] 4 (note 12) cutrng = 0 cutrng = 1 l l l 180 9 4.5 188 9.38 4.69 196 9.75 4.88 mv mv/lsb mv/lsb over current sense in auto mode class 0, class 3 class 1 class 2 class 4 l l l l 90 26 49 152 94 28 52 159 98 30 55 166 mv mv mv mv v lim active current limit in 802.3af compliant mode v sensen C v ee , icut12 = icut34 = hpen = 00h v ee = 55v (note 12) v ee < v out < a gnd C 29v a gnd C v out = 0v l l 204 40 212 220 100 mv mv v lim active current limit in high power mode hpen = 0fh, limn = c0h, v ee = 55v v out C v ee = 0v to 10v v ee + 23v < v out < a gnd C 29v a gnd C v out = 0v l l l 204 100 20 212 106 221 113 50 mv mv mv v lim active current limit in auto mode v out C v ee = 0v to 10v, v ee = 55v class 0 to class 3 class 4 l l 102 204 106 212 110 221 mv mv v min dc disconnect sense voltage v sensen C v ee , rdis = 0 v sensen C v ee , rdis = 1 l l 2.6 1.3 3.8 1.9 4.8 2.41 mv mv v sc short-circuit sense v sensen C v ee C v lim , rdis = 0 v sensen C v ee C v lim , rdis = 1 l l 160 75 200 100 255 135 mv mv port current readback resolution no missing codes, fast_iv = 0 14 bits lsb weight v sensen C v ee 30.5 v/lsb 50-60hz noise rejection (note 7) 30 db port voltage readback resolution no missing codes, fast_iv = 0 14 bits lsb weight a gnd C v outn 5.835 mv/lsb 50-60hz noise rejection (note 7) 30 db digital interface v ild digital input low voltage (note 6) l 0.8 v v ihd digital input high voltage (note 6) l 2.2 v digital output low voltage i sdaout = 3ma, i int = 3ma i sdaout = 5ma, i int = 5ma l l 0.4 0.7 v v internal pull-up to v dd ad n , shdn n , reset, msd 50 k internal pull-down to d gnd auto, mid 50 k electric a l ch a r a cteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a gnd C v ee = 54v, a gnd = d gnd , and v dd C d gnd = 3.3v unless otherwise noted. (notes 3, 4)
ltc4266 4266fa symbol parameter conditions min typ max units timing characteristics t det detection time beginning to end of detection (note 7) l 270 290 310 ms t detdly detection delay from pd connected to port to detection complete (note 7) l 300 470 ms t cle1 first class event duration (note 7) l 11 12 13 ms t me1 first mark event duration (notes 7, 11) l 6.8 8.6 10.3 ms t cle2 second class event duration (note 7) l 11 12 13 ms t me2 second mark event duration (note 7) l 19 22 ms t cle3 third class event duration c port = 0.6f (note 7) l 0.1 ms t pon power on delay in auto mode from end of valid detect to application of power to port (note 7) l 60 ms turn on rise time (a gnd C v out ): 10% to 90% of (a gnd C v ee ), c port = 0.15f (note 7) l 15 24 s turn on ramp rate c port = 0.15f (note 7) l 10 v/s fault delay from i cut fault to next detect l 1.0 1.1 s midspan mode detection backoff rport = 15.5k? (note 7) l 2.3 2.5 2.7 s power removal detection delay from power removal after t dis to next detect (note 7) l 1.0 1.3 2.5 s t start maximum current limit duration during port start-up t start1 = 0, t start0 = 0 (notes 7, 12) l 52 62.5 66 ms t lim , t icut maximum current limit duration after port start-up t icut1 = 0, t icut0 = 0 (notes 7, 12) l 52 62.5 66 ms maximum current limit duty cycle (note 7) l 5.8 6.3 6.7 % t mps maintain power signature (mps) pulse width sensitivity current pulse width to reset disconnect timer (notes 7, 8) l 1.6 3.6 ms t dis maintain power signature (mps) dropout time t conf [1:0] = 00b (notes 5, 12) l 320 350 380 ms t msd masked shut down delay (note 7) l 6.5 s t shdn port shut down delay (note 7) l 6.5 s i 2 c watchdog timer duration l 1.5 2 3 s minimum pulse width for masked shut down (note 7) l 3 s minimum pulse width for shdn (note 7) l 3 s minimum pulse width for reset (note 7) l 4.5 s electric a l ch a r a ct eristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a gnd C v ee = 54v, a gnd = d gnd , and v dd C d gnd = 3.3v unless otherwise noted. (notes 3, 4)
ltc4266 4266fa symbol parameter conditions min typ max units i 2 c timing clock frequency (note 7) l 1 mhz t 1 bus free time figure 5 (notes 7, 9) l 480 ns t 2 start hold time figure 5 (notes 7, 9) l 240 ns t 3 scl low time figure 5 (notes 7, 9) l 480 ns t 4 scl high time figure 5 (notes 7, 9) l 240 ns t 5 data hold time figure 5 (notes 7, 9) data into chip data out of chip l l 60 120 ns ns t 6 data set-up time figure 5 (notes 7, 9) l 80 ns t 7 start set-up time figure 5 (notes 7, 9) l 240 ns t 8 stop set-up time figure 5 (notes 7, 9) l 240 ns t r scl, sdain rise time figure 5 (notes 7, 9) l 120 ns t f scl, sdain fall time figure 5 (notes 7, 9) l 60 ns fault present to int pin low (notes 7, 9, 10) l 150 ns stop condition to int pin low (notes 7, 9, 10) l 1.5 s ara to int pin high time (notes 7, 9) l 1.5 s scl fall to ack low (notes 7, 9) l 120 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 140c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 3: all currents into device pins are positive; all currents out of device pins are negative. note 4: the ltc4266 operates with a negative supply voltage (with respect to ground). to avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. note 5: t dis is the same as t mpdo defined by ieee 802.3at. note 6: the ltc4266 digital interface operates with respect to d gnd . all logic levels are measured with respect to d gnd . note 7: guaranteed by design, not subject to test. note 8: the ieee 802.3af specification allows a pd to present its maintain power signature (mps) on an intermittent basis without being disconnected. in order to stay powered, the pd must present the mps for t mps within any t mpdo time window. note 9: values measured at v ild(max) and v ihd(min) . note 10: if fault condition occurs during an i 2 c transaction, the int pin will not be pulled down until a stop condition is present on the i 2 c bus. note 11: load characteristic of the ltc4266 during mark: 7v < (a gnd C v outn ) < 10v or i out < 50a note 12: see the ltc4266 software programming documentation for information on serial bus usage and device configuration and status registers. electric a l ch a r a cteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a gnd C v ee = 54v, a gnd = d gnd , and v dd C d gnd = 3.3v unless otherwise noted. (notes 3, 4)
ltc4266 4266fa t ypic a l p er f or ma nce c h a r a cteristics power on sequence in auto mode powering up into a 180f load 802.3af classification in auto mode 2-event classification in auto mode classification transient response to 40ma load step classification current compliance v dd supply current vs voltage 100ms/div ?70 ?60 port voltage (v) 10 0 ?10 ?20 ?30 ?40 ?50 4266 g01 port 1 v dd = 3.3v v ee = ?54v forced current detection forced voltage detection 802.3af classification power on gnd v ee 5ms/div gnd 0ma 4266 g02 v ee v ee gate voltage 10v/div port current 200 ma/div port voltage 20v/div foldback fet on 425ma current limit load fully charged v dd = 3.3v v ee = ?54v 5ms/div v ee ?18.4 port voltage 10v/div gnd 4266 g03 port 1 v dd = 3.3v v ee = ?55v pd is class 1 10ms/div v ee ?17.6 port voltage 10v/div gnd 4266 g04 port 1 v dd = 3.3v v ee = ?55v pd is class 4 1st class event 2nd class event 50s/div 40ma 0ma 4266 g05 ?20v port voltage 1v/div port current 20ma/div v dd = 3.3v v ee = ?54v classification current ?20 classification voltage (v) ?18 ?16 ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 0 10 20 30 4266 g06 40 50 60 70 v dd = 3.3v v ee = ?54v t a = 25c v dd supply voltage (v) 2.7 0.8 i dd supply current (ma) 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2.9 3.1 3.3 3.5 4266 g07 3.7 3.9 4.1 4.3 ?40c 25c 85c v ee supply current vs voltage 802.3at i lim threshold vs temperature v ee supply voltage (v) ?60 2.0 i ee supply current (ma) 2.1 2.2 2.3 2.4 ?55 ?50 ?45 ?40 4266 g08 ?35 ?30 ?25 ?20 ?40c 25c 85c temperature (c) ?40 210 v lim (mv) i lim (ma) 211 213 212 214 215 840 844 852 848 856 860 0 40 4266 g09 ?80 120 v dd = 3.3v v ee = ?54v r sense = 0.25 reg 48h = c0h
ltc4266 4266fa typic a l per f or ma nce ch a r a cteristics 802.3af i lim threshold vs temperature dc disconnect threshold vs temperature current limit foldback adc noise histogram current readback in fast mode adc integral nonlinearity current readback in fast mode temperature (c) ?40 105.00 v lim (mv) i lim (ma) 106.50 105.75 107.25 108.00 420 423 426 429 432 0 40 4266 g10 80 120 v dd = 3.3v v ee = ?54v r sense = 0.25 reg 48h = 80h port 1 802.3at i cut threshold vs temperature 802.3af i cut threshold vs temperature temperature (c) ?40 158 v cut (mv) i cut (ma) 161 160 159 162 163 630 636 640 648 644 652 0 40 4266 g11 80 120 v dd = 3.3v v ee = ?54v r sense = 0.25 reg 47h = e2h port 1 temperature (c) ?40 93.00 v cut (mv) i cut (ma) 94.50 93.75 95.25 96.00 372 375 378 381 384 0 40 4266 g12 80 120 v dd = 3.3v v ee = ?54v r sense = 0.25 reg 47h = d4h port 1 temperature (c) ?40 v min (mv) i min (mv) 7.00 7.50 7.25 7.75 8.00 1.7500 1.8125 1.8750 1.9375 2.0000 0 40 4266 g13 80 120 v dd = 3.3v v ee = ?54v r sense = 0.25 reg 47h = e2h port 1 v outn (v) ?54 0 i lim (ma) v lim (mv) 900 800 700 600 500 400 300 200 100 0 225 200 175 150 125 100 75 50 25 ?36?45 ?27 4266 g14 ?18 ?9 0 v dd = 3.3v v ee = ?54v r sense = 0.25 reg 48h = c0h adc output 191 0 b in count 400 350 300 250 200 150 100 50 193192 194 4266 g15 195 196 v sensen ? v ee = 110.4mv current sense resistor input voltage (mv) 0 adc integral nonlinearity (lsbs) 0 0.5 400 4266 g16 ?0.5 ?1.0 100 200 250 500 1.0 300 50 150 450 350
ltc4266 4266fa typic a l per f or ma nce ch a r a cteristics adc noise histogram current readback in slow mode adc integral nonlinearity current readback in slow mode adc noise histogram port v oltage readback in fast mode adc integral nonlinearity voltage readback in fast mode adc noise histogram port v oltage readback in slow mode adc integral nonlinearity v oltage readback in slow mode int and sda out pull down voltage vs load current mosfet gate drive with fast pull down adc output 0 b in count 300 250 200 150 100 50 6139 6141 4266 g17 6143 6145 6147 v sensen ? v ee = 110.4mv adc output 260 0 b in count 600 500 400 300 200 100 262261 263 4266 g19 264 265 a gnd ? v outn = 48.3v adc output 8532 0 b in count 600 500 400 300 200 100 8534 8533 8535 4266 g21 8536 a gnd ? v outn = 48.3v load current (ma) 0 0 pull down voltage (v) 3 2.5 2 1.5 1 0.5 105 15 4266 g23 20 25 30 35 40 100s/div gnd 0ma 4266 g24 v ee v ee port current 500ma/div gate voltage 10v/div port voltage 20v/div current limit 50 fault removed 50 fault applied v dd = 3.3v v ee = ?54v fast pull down current sense resistor input voltage (mv) 0 adc integral nonlinearity (lsbs) 0 0.5 400 4266 g18 ?0.5 ?1.0 100 200 250 500 1.0 300 50 150 450 350 port voltage (v) 0 adc integral nonlinearity (lsbs) 0 0.5 50 4266 g20 ?0.5 ?1.0 20 30 60 1.0 40 10 port voltage (v) 0 adc integral nonlinearity (lsbs) 0 0.5 50 4266 g22 ?0.5 ?1.0 20 30 60 1.0 40 10
ltc4266 0 4266fa t est t i m ing di a gr am s figure 1. detect, class and turn-on timing in auto or semiauto modes figure 2. current limit timing figure 3. dc disconnect timing figure 4. shut down delay timing figure 5. i 2 c interface timing v lim v cut 0v v sensen to v ee int 4266 f02 t start , t icut scl sda t 1 t 2 t 3 t r t f t 5 t 6 t 7 t 8 t 4 4266 f05 v min v sensen to v ee int t dis t mps 4266 f03 v portn int t detdly v oc v ee t det t me1 t me2 v mark v class 15.5v 20.5v t cle1 t cle2 t cle3 pd connected 0v 4266 f01 forced-current classification t pon forced- voltage v gaten v ee msd or shdnn t shdn t msd 4266 f04
ltc4266 4266fa i 2 c t i m ing di a gr am s figure 6. writing to a register figure 7. reading from a register scl sda 4266 f06 0 01 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 a2 a1 a0 r/w ack d7 d6 d5 d4 d3 d2 d1 d0 ack ack start by master ack by slave ack by slave ack by slave frame 1 serial bus address byte frame 2 register address byte frame 3 data byte stop by master scl sda 0 01 ad3 ad2 ad1 ad0 a7 a6 a5 a4 a3 a2 a1 a0 r/w ack ack 0 01 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack ack start by master ack by slave ack by slave 4266 f07 stop by master repeated start by master ack by slave no ack by master frame 1 serial bus address byte frame 2 register address byte frame 1 serial bus address byte frame 2 data byte
ltc4266 4266fa figure 8. reading the interrupt register (short form) figure 9. reading from alert response address scl sda 4266 f08 0 1 0 ad3 ad2 ad1 ad0 d7 d6 d5 d4 d3 d2 d1 d0 r/w ack ack start by master ack by slave no ack by master frame 1 serial bus address byte frame 2 data byte stop by master scl sda 4266 f09 0 0 11 0 ad30 0 00 1 ad2 ad1 ad0 r/w ack ack1 start by master ack by slave no ack by master frame 1 alert response address byte frame 2 serial bus address byte stop by master i 2 c t im ing d i a gr am s
ltc4266 4266fa p in functions reset: chip reset, active low. when the reset pin is low, the ltc4266 is held inactive with all ports off and all internal registers reset to their power-up states. when reset is pulled high, the ltc4266 begins normal opera- tion. reset can be connected to an external capacitor or rc network to provide a power turn-on delay. internal filtering of the reset pin prevents glitches less than 1s wide from resetting the ltc4266. internally pulled up to v dd . mid: midspan mode input. when high, the ltc4266 acts as a midspan device. internally pulled down to d gnd . int: interrupt output, open drain. int will pull low when any one of several events occur in the ltc4266. it will return to a high impedance state when bits 6 or 7 are set in the reset pb register (1ah). the int signal can be used to generate an interrupt to the host processor, eliminating the need for continuous software polling. individual int events can be disabled using the int mask register (01h). see register functions and applications information for more information. the int pin is only updated between i 2 c transactions. scl: serial clock input. high impedance clock input for the i 2 c serial interface bus. scl must be tied high if not used. sdaout: serial data output, open drain data output for the i 2 c serial interface bus. the ltc4266 uses two pins to implement the bidirectional sda function to simplify optoisolation of the i 2 c bus. to implement a standard bidirectional sda pin, tie sdaout and sdain together. sdaout should be grounded or left floating if not used. see applications information for more information. sdain: serial data input. high impedance data input for the i 2 c serial interface bus. the ltc4266 uses two pins to implement the bidirectional sda function to simplify optoisolation of the i 2 c bus. to implement a standard bidirectional sda pin, tie sdaout and sdain together. sdain must be tied high if not used. see applications information for more information. ad3: address bit 3. tie the address pins high or low to set the i 2 c serial address to which the ltc4266 responds. this address will be 010a 3 a 2 a 1 a 0 b. internally pulled up to v dd . ad2: address bit 2. see ad3. ad1: address bit 1. see ad3. ad0: address bit 0. see ad3. nc, dnc: all pins identified with nc or dnc must be left unconnected. dgnd: digital ground. dgnd is the return for the v dd supply. v dd : logic power supply. connect to a 3.3v power supply relative to dgnd. v dd must be bypassed to dgnd near the ltc4266 with at least a 0.1f capacitor. shdn1: shutdown port 1, active low. when pulled low, shdn1 shuts down port 1, regardless of the state of the internal registers. pulling shdn1 low is equivalent to set- ting the reset port 1 bit in the reset pushbutton register (1ah). internal filtering of the shdn1 pin prevents glitches less than 1s wide from reseting the port. internally pulled up to v dd . shdn2: shutdown port 2, active low. see shdn1. shdn3: shutdown port 3, active low. see shdn1. shdn4: shutdown port 4, active low. see shdn1. agnd: analog ground. agnd is the return for the v ee supply. sense4: port 4 current sense input. sense4 monitors the external mosfet current via a 0.5? or 0.25 sense resistor between sense4 and v ee . whenever the voltage across the sense resistor exceeds the overcurrent detection threshold v cut , the current limit fault timer counts up. if the voltage across the sense resistor reaches the current limit threshold v lim , the gate4 pin voltage is lowered to maintain constant current in the external mosfet. see applications information for further details. if the port is unused, the sense4 pin must be tied to v ee .
ltc4266 4266fa pin f unctions gate4: port 4 gate drive. gate4 should be connected to the gate of the external mosfet for port 4. when the mosfet is turned on, the gate voltage is driven to 13v (typ) above v ee . during a current limit condition, the voltage at gate4 will be reduced to maintain constant current through the external mosfet. if the fault timer expires, gate4 is pulled down, turning the mosfet off and recording a t cut or t start event. if the port is unused, float the gate4 pin. out4: port 4 output voltage monitor. out4 should be connected to the output port. a current limit foldback circuit limits the power dissipation in the external mosfet by reducing the current limit threshold when the drain-to- source voltage exceeds 10v. the port 4 power good bit is set when the voltage from out4 to v ee drops below 2.4v (typ). a 500k resistor is connected internally from out4 to agnd when the port is idle. if the port is unused, out4 pin must be floated. sense3: port 3 current sense input. see sense4. gate3: port 3 gate drive. see gate4. out3: port 3 output voltage monitor. see out4. v ee : main supply input. connect to a C45v to C57v supply, relative to agnd. sense2: port 2 current sense input. see sense4. gate2: port 2 gate drive. see gate4. out2: port 2 output voltage monitor. see out4. sense1: port 1 current sense input. see sense4. gate1: port 1 gate drive. see gate 4. out1: port 1 output voltage monitor. see out4. auto: auto mode input. auto mode allows the ltc4266 to detect and power up a pd even if there is no host con- troller present on the i 2 c bus. the voltage of the auto pin determines the state of the internal registers when the ltc4266 is reset or comes out of v dd uvlo (see the register map). the states of these register bits can sub- sequently be changed via the i 2 c interface. the real-time state of the auto pin is read at bit 0 in the pin status register (11h). internally pulled down to d gnd . must be tied locally to either v dd or dgnd. msd: maskable shutdown input. active low. when pulled low, all ports that have their corresponding mask bit set in the mconfig register (17h) will be reset, equivalent to pulling the shdn pin low . internal filtering of the msd pin prevents glitches less than 1s wide from resetting ports. internally pulled up to v dd .
ltc4266 4266fa o per a tion figure 10. power over ethernet system diagram 4266 f10 s1b s1b smaj58a 0.22f 100v x7r 1 f 100v x7r tx rx rx tx smaj58a 58v data pair data pair v ee sense gate out v dd int scl sdain sdaout 0.25 irfm120a spare pair spare pair 1/4 ltc4266 dgnd agnd i 2 c 3.3v interrupt ?48v cat 5 20 max roundtrip 0.05f max rj45 4 5 4 5 1 2 1 2 3 6 3 6 7 8 7 8 rj45 1n4002 s4 1n4002 s4 pse pd r class ?48v in pwrgd ?48v out ltc4265 gnd dc/dc converter 5 f c in 300f + ? v out gnd 0.1 f overview power over ethernet, or poe, is a standard protocol for sending dc power over copper ethernet data wiring. the ieee group that administers the 802.3 ethernet data standards added poe powering capability in 2003. this original poe spec, known as 802.3af, allowed for 48v dc power at up to 13w. this initial spec was widely popular, but 13w was not adequate for some requirements. in 2009, the ieee released a new standard, known as 802.3at or poe+, increasing the voltage and current requirements to provide 25w of power. the ieee standard also defines poe terminology. a device that provides power to the network is known as a pse, or power sourcing equipment, while a device that draws power from the network is known as a pd, or powered device. pses come in two types: endpoints (typically network switches or routers), which provide data and power; and midspans, which provide power but pass through data. midspans are typically used to add poe capability to existing non-poe networks. pds are typically ip phones, wireless access points, security cameras, and similar devices, but could be nearly anything that runs from 25w or less and includes an rj45-style network connector. the ltc4266 is a third-generation quad pse controller that implements four pse ports in either an endpoint or midspan design. virtually all necessary circuitry is included to implement a ieee 802.3at compliant pse design, requir - ing only an external power mosfet and sense resistor per channel; these minimize power loss compared to alterna - tive designs with on-board mosfets and increase system reliability in the event a single channel is damaged. poe basics common ethernet data connections consist of two or four twisted pairs of copper wire (commonly known as cat-5 cable), transformer-coupled at each end to avoid ground loops. poe systems take advantage of this coupling ar - rangement by applying voltage between the center-taps of the data transformers to transmit power from the pse to the pd without affecting data transmission. figure 10 shows a high-level poe system schematic. to avoid damaging legacy data equipment that does not expect to see dc voltage, the poe spec defines a protocol that determines when the pse may apply and remove power. valid pds are required to have a specific 25k common-mode resistance at their input. when such a pd is connected to the cable, the pse detects this signature resistance and turns on the power. when the pd is later disconnected, the pse senses the open circuit and turns power off. the pse also turns off power in the event of a current fault or short circuit. when a pd is detected, the pse optionally looks for a classification signature that tells the pse the maximum power the pd will draw. the pse can use this information to allocate power among several ports, police the current consumption of the pd, or to reject a pd that will draw
ltc4266 4266fa o per a tion more power that the pse has available. the classification step is optional; if a pse chooses not to classify a pd, it must assume that the pd is a 13w (full 802.3af power) device. new in 802.3at the newer 802.3at standard supersedes 802.3af and brings several new features: ? a pd may draw as much as 25.5w. such pds (and the pses that support them) are known as type 2. older 13w 802.3af equipment is classified as type 1. type 1 pds will work with all pses; type 2 pds may require type 2 pses to work properly. the ltc4266 is designed to work in both type 1 and type 2 pse designs, and also supports non-standard configurations at higher power levels. ? the classification protocol is expanded to allow type 2 pses to detect type 2 pds, and to allow type 2 pds to determine if they are connected to a type 2 pse. two versions of the new classification protocol are avail - able: an expanded version of the 802.3af class pulse protocol, and an alternate method integrated with the existing lldp protocol (using the ethernet data path). the ltc4266 fully supports the new class pulse protocol and is also compatible with the lldp protocol (which is implemented in the data communications layer, not in the poe circuitry). ? fault protection current levels and timing are adjusted to reduce peak power in the mosfet during a fault; this allows the new 25.5w power levels to be reached using the same mosfets as older 13w designs. b ackwards c ompatibility the ltc4266 is designed to be backward compatible with earlier pse chips in both software and pin functions. exist - ing systems using either the ltc4258 or ltc4259a (or compatible) devices can be substituted with the ltc4266 without software or pcb layout changes; only minor bom changes are required to implement a fully compliant 802.3at design. because of the backwards compatibility features, some of the internal registers are redundant or unused when the ltc4266 is operated as recommended. for more details on usage in compatibility mode, refer to the ltc4258/ ltc4259a device datasheets. special compatibility mode notes ? the ltc4266 can use either 0.5 or 0.25 sense resistors, while the ltc425x chips always used 0.5. to maintain compatibility, if the auto pin is low when the ltc4266 powers up it assumes the sense resistor is 0.5; if it is high at power up, the ltc4266 assumes 0.25. the resistor value setting can be reconfigured at any time after power up. in particular, systems that use 0.25 sense resistors and have auto tied low must reconfigure the resistor settings after power up. ? the ltc4259a included both ac and dc disconnect sensing circuitry, but the ltc4266 has only dc discon - nect sensing. for the sake of compatibility, register bits used to enable ac disconnect in the ltc4259a are implemented in the ltc4266, but they simply mirror the bits used for dc disconnect. ? the ltc4258 and ltc4259a required 10k resistors between the outn pins and the drains of the external mosfets. these resistors must be shorted or replaced with zero ohm jumpers when using the ltc4266. ? the ltc4258 and ltc4259a included a byp pin, de - co upled to agnd with 0.1f. this pin changes to the mid pin on the ltc4266. the capacitor should be removed for endspan applications, or replaced with a zero ohm jumper for midspan applications.
ltc4266 4266fa applic a tions i n f or ma tion operating modes the ltc4266 includes four independent ports, each of which can operate in one of four modes: manual, semi- auto, auto, or shutdown. ? in manual mode, the port waits for instructions from the host system before taking any action. it runs a single detection or classification cycle when commanded to by the host, and reports the result in its port status register. the host system can command the port to turn on or off the power at any time. ? in semi-auto mode, the port repeatedly attempts to detect and classify any pd attached to it. it reports the status of these attempts back to the host, and waits for a command from the host before turning on power to the port. the host must enable detection (and optionally classification) for the port before detection will start. ? auto mode operates the same as semi-auto mode except that it will automatically turn on the power to the port if detection is successful. ? in shutdown mode, the port is disabled and will not detect or power a pd. regardless of which mode it is in, the ltc4266 will remove power automatically from any port that generates a current limit fault. it will also automatically remove power from any port that generates a disconnect event if disconnect detection is enabled. the host controller may also com - mand the port to remove power at any time. power-on reset and the auto/mid pins the initial ltc4266 configuration depends on the state of the auto and mid pins during reset. reset occurs at power-up, or whenever the reset pin is pulled low or the global reset all bit is set. note that the auto pin is only sampled when a reset occurs. changing the state of auto or mid after power-up will not change the port behavior of the ltc4266 until a reset occurs. although typically used with a host controller, the ltc4266 can also be used in a standalone mode with no connection to the serial interface. if there is no host present, the auto pin should be tied high so that, at reset, all ports will be configured to operate automatically. each port will detect and classify repeatedly until a pd is discovered, set i cut and i lim according to the classification results, apply power after successful detection, and remove power when a pd is disconnected. similarly, if the standalone application is a midspan, the mid pin should be tied high to enable correct midspan detection timing. table 1 shows the i cut and i lim values that will be automatically set in standalone mode, based on the dis- covered class. table 1. i cut and i lim values in standalone mode class i cut i lim class 1 112ma 425ma class 2 206ma 425ma class 3 or class 0 375ma 425ma class 4 638ma 850ma the automatic setting of the i cut and i lim values only oc- curs if the ltc4266 is reset with the auto pin high. detection detection overview to avoid damaging network devices that were not designed to tolerate dc voltage, a pse must determine whether the connected device is a real pd before applying power. the ieee specification requires that a valid pd have a common- mode resistance of 25k? 5% at any port voltage below 10v. the pse must accept resistances that fall between 19k? and 26.5k?, and it must reject resistances above 33k? or below 15k? (shaded regions in figure 11). the pse may choose to accept or reject resistances in the undefined areas between the must-accept and must-reject ranges. in particular, the pse must reject standard computer network ports, many of which have 150 common-mode termination resistors that will be damaged if power is ap - plied to them (the black region at the left of figure 11). resistance pd pse 0 10k 15k 4266 f11 19k 26.5k 26.25k 23.75k 150 (nic) 20k 30k 33k figure 11. ieee 802.3af signature resistance ranges
ltc4266 4266fa a pplic a tions in f or ma tion 4-point detection the ltc4266 uses a 4-point detection method to discover pds. false-positive detections are minimized by check - ing for signature resistance with both forced-current and forced-voltage measurements. initially, two test currents are forced onto the port (via the outn pin) and the resulting voltages are measured. the detection circuitry subtracts the two v-i points to determine the resistive slope while removing offset caused by series diodes or leakage at the port (see figure 12). if the forced-current detection yields a valid signature resistance, two test voltages are then forced onto the port and the resulting currents are measured and subtracted. both methods must report valid resistances for the port to report a valid detection. pd signature resistances between 17k and 29k (typically) are detected as valid and reported as detect good in the corresponding port status register. values outside this range, including open and short circuits, are also reported. if the port measures less than 1v at the first forced-current test, the detection cycle will abort and short circuit will be reported. table 2 shows the possible detection results. table 2. detection status measured pd signature detection result incomplete or not yet tested detect status unknown <2.4k short circuit capacitance > 2.7f cpd too high 2.4k < r pd < 17k rsig too low 17k < r pd < 29k detect good >29k rsig too high >50k open circuit voltage > 10v port voltage outside detect range operating modes the ports operating mode determines when the ltc4266 runs a detection cycle. in manual mode, the port will idle until the host orders a detect cycle. it will then run detection, report the results, and return to idle to wait for another command. in semi-auto mode, the ltc4266 autonomously polls a port for pds, but it will not apply power until commanded to do so by the host. the port status register is updated at the end of each detection cycle. if a valid signature resistance is detected and classification is enabled, the port will classify the pd and report that result as well. the port will then wait for at least 100ms (or 2 seconds if midspan mode is enabled), and will repeat the detection cycle to ensure that the data in the port status register is up-to-date. if the port is in semi-auto mode and high power opera- tion is enabled, the port will not turn on in response to a power-on command unless the current detect result is detect good. any other detect result will generate a t start fault if a power-on command is received. if the port is not in high power mode, it will ignore the detection result and apply power when commanded, maintaining backwards compatibility with the ltc4259a. behavior in auto mode is similar to semi-auto; however, after detect good is reported and the port is classified (if classification is enabled), it is automatically powered on without further intervention. in standalone mode, the i cut and i lim thresholds are automatically set in auto mode; see the power-on reset and the auto pin section for more information. the signature detection circuitry is disabled when the port is initially powered up with the auto pin low, in shutdown mode, or when the corresponding detect enable bit is cleared. detection of legacy pds proprietary pds that predate the original ieee 802.3af standard are commonly referred to today as legacy de - vices. one type of legacy pd uses a large common mode figure 12. pd detection first detection point second detection point valid pd 25k slope 275 165 current (a) 0v-2v offset voltage 4266 f12
ltc4266 4266fa a pplic a tions in f or ma tion capacitance (>10f) as the detection signature. note that pds in this range of capacitance are defined as invalid, so a pse that detects legacy pds is technically noncompliant with the ieee spec. the ltc4266 can be configured to detect this type of legacy pd. legacy detection is disabled by default, but can be manually enabled on a per-port basis. when enabled, the port will report detect good when it sees either a valid ieee pd or a high-capacitance legacy pd. with legacy mode disabled, only valid ieee pds will be recognized. c lassification 802.3af classification a pd can optionally present a classification signature to the pse to indicate the maximum power it will draw while operating. the ieee specification defines this signature as a constant current draw when the pse port voltage is in the v class range (between 15.5v and 20.5v), with the current level indicating one of 5 possible pd classes. figure 14 shows a typical pd load line, starting with the slope of the 25k? signature resistor below 10v, then transitioning to the classification signature current (in this case, class 3) in the v class range. table 3 shows the possible clas- sification values. table 3. classification values class result class 0 no class signature present; treat like class 3 class 1 3w class 2 7w class 3 13w class 4 25.5w (type 2) if classification is enabled, the port will classify the pd immediately after a successful detection cycle in semi-auto or auto modes, or when commanded to in manual mode. it measures the pd classification signature by applying 18v for 12ms (both values typical) to the port via the out n pin and measuring the resulting current; it then reports the discovered class in the port status register. if the ltc4266 was reset with the auto pin high and the port is in auto mode, it will additionally use the classification result to set the i cut and i lim thresholds. see the power-on reset and the auto/mid pin section for more information. the classification circuitry is disabled when the port is initially powered up with the auto pin low, in shutdown mode, or when the corresponding class enable bit is cleared. 802.3at 2-event classification the 802.3at spec defines two methods of classifying a type 2 pd. one method adds extra fields to the ethernet lldp data protocol; although the ltc4266 is compatible with this classification method, it cannot perform classification directly since it doesnt have access to the data path. lldp classification requires the pse to power the pd as a standard 802.3af (type 1) device. it then waits for the host to perform lldp communication with the pd and update the pse port data. the ltc4266 supports chang - ing the i lim and i cut levels on the fly, allowing the host to complete lldp classification. the second 802.3at classification method, known as 2- event classification or ping-pong, is fully supported by the ltc4266. a type 2 pd that is requesting more than 13w will indicate class 4 during normal 802.3af classification. if the ltc4266 sees class 4, it forces the port to a speci - fied lower voltage (called the mark voltage, typically 9v), pauses briefly, and then re-runs classification to verify the class 4 reading (figure 1). it also sets a bit in the high voltage (v class ) 0 current (ma) 60 50 40 30 20 10 0 5 10 15 20 4266 f13 25 typical class 3 pd load line 48ma 33ma pse load line 23ma 14.5ma 6.5ma class 4 class 2 class 1 class 0 class 3 over current figure 13. pd classification
ltc4266 0 4266fa a pplic a tions in f or ma tion power status register to indicate that it ran the second classification cycle. the second cycle alerts the pd that it is connected to a type 2 pse which can supply type 2 power levels. 2-event ping-pong classification is enabled by setting a bit in the ports high power mode register. note that a ping- pong enabled port only runs the second classification cycle when it detects a class 4 device; if the first cycle returns class 0 to 3, the port assumes it is connected to a type 1 pd and does not run the second classification cycle. invalid type 2 class combinations the 802.3at spec defines a type 2 pd class signature as two consecutive class 4 results; a class 4 followed by a class 0-3 is not a valid signature. in auto mode, the ltc4266 will power a detected pd regardless of the clas - sification results, with one exception: if the pd presents an invalid type 2 signature (class 4 followed by class 0 to 3), the ltc4266 will not provide power and will restart the detection process. to aid in diagnosis, the port status register will always report the results of the last class pulse, so an invalid class 4Cclass 2 combination would report a second class pulse was run in the high power status register (which implies that the first cycle found class 4), and class 2 in the port status register. power control external mosfet, sense r summary the primary function of the ltc4266 is to control the delivery of power to the pse port. it does this by control - ling the gate drive voltage of an external power mosfet while monitoring the current via an external sense resis - tor and the output voltage at the out pin. this circuitry serves to couple the raw v ee input supply to the port in a controlled manner that satisfies the pds power needs while minimizing power dissipation in the mosfet and disturbances on the v ee backplane. the ltc4266 is designed to use 0.25? sense resistors to minimize power dissipation. it also supports 0.5? sense resistors, which are the default when ltc4258/ltc4259a compatibility is desired. inrush control once the command has been given to turn on a port, the ltc4266 ramps up the gate pin of that ports external mosfet in a controlled manner. under normal power-up circumstances, the mosfet gate will rise until the port current reaches the inrush current limit level (typically 450ma), at which point the gate pin will be servoed to maintain the specified i inrush current. during this inrush period, a timer (t start ) runs. when output charging is complete, the port current will fall and the gate pin will be allowed to continue rising to fully enhance the mosfet and minimize its on-resistance. the final v gs is nominally 13v. if the t start timer expires before the inrush period completes, the port will be turned back off and a t start fault reported. current limit each ltc4266 port includes two current limiting thresholds (i cut and i lim ), each with a corresponding timer (t cut and t lim ). setting the i cut and i lim thresholds depends on several factors: the class of the pd, the voltage of the main supply (v ee ), the type of pse (1 or 2), the sense resistor (0.5 or 0.25), the soa of the mosfet, and whether or not the system is required to implement class enforcement. per the ieee spec, the ltc4266 will allow the port cur- rent to exceed i cut for a limited period of time before removing power from the port, whereas it will actively control the mosfet gate drive to keep the port current below i lim . the port does not take any action to limit the current when only the i cut threshold is exceeded, but does start the t cut timer. the t lim timer starts when the i lim threshold is exceeded and current limit is active. if the current drops below the i cut current threshold before its timer expires, the t cut timer counts back down, but at 1/16 the rate that it counts up. this allows the current limit circuitry to tolerate intermittent overload signals with duty cycles below about 6%; longer duty cycle overloads will turn the port off. i cut is typically set to a lower value than i lim to allow the port to tolerate minor faults without current limiting.
ltc4266 4266fa a pplic a tions in f or ma tion per the ieee specification, the ltc4266 will automatically set i lim to 425ma (shown in bold in table 4) during inrush at port turn-on, and then switch to the programmed i lim setting once inrush has completed. to maintain ieee compliance, i lim should kept at 425ma for all type 1 pds, and 850ma if a type 2 pd is detected. i lim is automatically reset to 425ma when a port turns off. table 4. example current limit settings i lim (ma) internal register setting (hex) r sense = 0.5 r sense = 0.25 53 88 106 08 88 159 89 213 80 08 266 8a 319 09 89 372 8b 425 00 80 478 8e 531 92 8a 584 cb 638 10 90 744 d2 9a 850 40 c0 956 4a ca 1063 50 d0 1169 5a da 1275 60 e0 1488 52 49 1700 40 1913 4a 2125 50 2338 5a 2550 60 2975 52 i lim foldback the ltc4266 features a two-stage foldback circuit that reduces the port current if the port voltage falls below the normal operating voltage. this keeps mosfet power dissipation at safe levels for typical 802.3af mosfets, even at extended 802.3at power levels. current limit and foldback behavior are programmable on a per-port basis. figure 14 shows mosfet power dissipation with 802.3af- style foldback compared with a typical mosfet soa curve; figure 15 demonstrates how two-stage foldback keeps the fet within its soa under the same conditions. table 4 gives examples of recommended i lim register settings. the ltc4266 will support current levels well beyond the maximum values in the 802.3at specification. the shaded areas in table 4 indicate settings that may require a larger external mosfet, additional heat sinking, or a reduced t lim setting. pd voltage (v) at v pse = 58v 0 0.0 pse current (a) 0.2 0.4 0.6 10 20 30 40 4266 f14 50 0.8 1.0 0.1 0.3 0.5 0.7 0.9 60 802.3af foldback 2 x 802.3af foldback soa 75ms at 25c soa dc at 90c pd voltage (v) at v pse = 58v 0 0.0 pse current (a) 0.2 0.4 0.6 10 20 30 40 4266 f15 50 0.8 1.0 0.1 0.3 0.5 0.7 0.9 60 ltc4266 foldback 802.3af foldback soa dc at 90c soa 75ms at 90c soa 75ms at 25c figure 14. turn on currents vs fet safe operating area at 90c ambient figure 15. ltc4266 foldback vs fet safe operating area at 90c ambient
ltc4266 4266fa a pplic a tions in f or ma tion mosfet fault detection ltc4266 pse ports are designed to tolerate significant levels of abuse, but in extreme cases it is possible for the external mosfet to be damaged. a failed mosfet may short source to drain, which will make the port ap - pear to be on when it should be off; this condition may also cause the sense resistor to fuse open, turning off the port but causing the ltc4266 sense pin to rise to an abnormally high voltage. a failed mosfet may also short from gate to drain, causing the ltc4266 gate pin to rise to an abnormally high voltage. the ltc4266 sense and gate pins are designed to tolerate up to 80v faults without damage. if the ltc4266 sees any of these conditions for more than 180s, it disables all port functionality, reduces the gate drive pull-down current for the port and reports a fet bad fault. this is typically a permanent fault, but the host can attempt to recover by resetting the port, or by resetting the entire chip if a port reset fails to clear the fault. if the mosfet is in fact bad, the fault will quickly return, and the port will disable itself again. the remaining ports of the ltc4266 are unaffected. an open or missing mosfet will not trigger a fet bad fault, but will cause a t start fault if the ltc4266 attempts to turn on the port. voltage and current readback the ltc4266 measures the output voltage and current at each port with an internal a/d converter. port data is only valid when the port power is on. the converter has two modes: ? slow mode: 14 samples per second, 14.5 bits resolution ? fast mode: 440 samples per second, 9.5 bits resolution in fast mode, the least significant 5 bits of the lower byte are zeroes so that bit scaling is the same in both modes. disconnect the l tc4266 monitors the port to make sure that the pd continues to draw the minimum specified current. a dis - connect timer counts up whenever port current is below 7.5ma (typ), indicating that the pd has been disconnected. if the t dis timer expires, the port will be turned off and the disconnect bit in the fault event register will be set. if the current returns before the t dis timer runs out, the timer resets and will start counting from the beginning if the undercurrent condition returns. as long as the pd exceeds the minimum current level more often than t dis , it will stay powered. although not recommended, the dc disconnect feature can be disabled by clearing the corresponding enable bits. note that this defeats the protection mechanisms built into the ieee spec, since a powered port will stay powered after the pd is removed. if the still-powered port is subsequently connected to a non-poe data device, the device may be damaged. the ltc4266 does not include ac disconnect circuitry, but includes ac disconnect enable bits to maintain compat - ibility with the ltc4259a. if the ac disconnect enable bits are set, dc disconnect will be used. shutdown pins the ltc4266 includes a hardware shdn pin for each port. when a shdn pin is pulled to dgnd, the corresponding port will be shut off immediately. the port remains shut down until re-enabled via i 2 c or a device reset in auto mode. masked shutdown the ltc4266 provides a low latency port shedding fea - ture to quickly reduce the system load when required. by allowing a pre-determined set of ports to be turned off, the current on an overloaded main power supply can be reduced rapidly while keeping high priority devices pow - ered. each port can be configured to high or low priority; all low-priority ports will shut down within 6.5s after the msd pin is pulled low. if multiple ports in a ltc4266 device are shut down via msd, they are staggered by at least 0.55s to help reduce voltage transients on the main supply. if a port is turned off via msd, the corresponding detection and classification enable bits are cleared, so the port will remain off until the host explicitly re-enables detection.
ltc4266 4266fa serial d igital i nterface overview t h e ltc4266 communicates with the host using a standard smbus/i 2 c 2-wire interface. the ltc4266 is a slave-only device, and communicates with the host master using the standard smbus protocols. interrupts are signaled to the host via the int pin. the timing diagrams (figures 6 through 10) show typical communication waveforms and their timing relationships. more information about the smbus data protocols can be found at www.smbus.org. the ltc4266 requires both the v dd and v ee supply rails to be present for the serial interface to function. bus addressing the ltc4266s primary serial bus address is 010xxxxb, with the lower four bits set by the ad3-ad0 pins; this allows up to 16 ltc4266s on a single bus. all ltc4266s also respond to the address 0110000b, allowing the host to write the same command (typically configuration commands) to multiple ltc4266s in a single transaction. if the ltc4266 is asserting the int pin, it will also respond to the alert response address (0001100b) per the smbus spec. interrupts and smbalert most ltc4266 port events can be configured to trigger an interrupt, asserting the int pin and alerting the host to the event. this removes the need for the host to poll the ltc4266, minimizing serial bus traffic and conserving host cpu cycles. multiple ltc4266s can share a common int line, with the host using the smbalert protocol (ara) to determine which ltc4266 caused an interrupt. register description for information on serial bus usage and device configura - tion and status, refer to the ltc4266 software program- ming documentation. external component selection power supplies and bypassing the ltc4266 requires two supply voltages to operate. v dd requires 3.3v (nominally) relative to dgnd. v ee requires a negative voltage of between C44v and C57v for type 1 pses, or C50v to C57v for type 2 pses, relative to agnd. the relationship between the two grounds is not fi xed; agnd can be referenced to any level from v dd to dgnd, although it should typically be tied to either v dd or dgnd. v dd provides power for most of the internal ltc4266 cir- cu itry, and draws a maximum of 3ma. a ceramic decoupling cap of at least 0.1f should be placed from v dd to dgnd, as close as practical to each ltc4266 chip. figure 16 shows a three component low dropout regulator for a negative supply to dgnd generated from the negative v ee supply. v dd is tied to agnd and dgnd is negative referenced to agnd. this regulator drives a single ltc4266 device. in figure 17, dgnd is tied to agnd in this boost converter circuit for a positive v dd supply of 3.3v above agnd. this circuit can drive multiple ltc4266 devices and opto couplers. a pplic a tions in f or ma tion 4266 f16 r5 750k d1 cmhz4687-4.3v c1 0.1 f q2 cmpta92 v ee v dd ltc4266 agnd v ee agnd dgnd figure 16. negative ldo to dgnd v ee is the main supply that provides power to the pds. because it supplies a relatively large amount of power and is subject to significant current transients, it requires more design care than a simple logic supply. for minimum ir loss and best system efficiency, set v ee near maximum amplitude (57v), leaving enough margin to account for transient over- or undershoot, temperature drift, and the line regulation specs of the particular power supply used. bypass capacitance between agnd and v ee is very im- portant for reliable operation. if a short circuit occurs at one of the output ports it can take as long as 1s for the ltc4266 to begin regulating the current. during this time the current is limited only by the small impedances in the circuit and a high current spike typically occurs, causing a
ltc4266 4266fa a pplic a tions in f or ma tion voltage transient on the v ee supply and possibly causing the ltc4266 to reset due to a uvlo fault. a 1f, 100v x7r capacitor placed near the v ee pin is recommended to minimize spurious resets. isolating the serial bus the ltc4266 includes a split sda pin (sdain and sdaout) to ease opto-isolation of the bidirectional sda line. ieee 802.3 ethernet specifications require that network segments (including poe circuitry) be electrically isolated from the chassis ground of each network interface device. however, network segments are not required to be isolated from each other, provided that the segments are connected to devices residing within a single building on a single power distribution system. for simple devices such as small poe switches, the isola - tion requirement can be met by using an isolated main power supply for the entire device. this strategy can be used if the device has no electrically conducting ports other than twisted-pair ethernet. in this case, the sdain and sdaout pins can be tied together and will act as a standard i 2 c/smbus sda pin. if the device is part of a larger system, contains additional external non-ethernet ports, or must be referenced to protective ground for some other reason, the power over ethernet subsystem (including all ltc4266s) must be electrically isolated from the rest of the system. figure 18 shows a typical isolated serial interface. the sdaout pin of the ltc4266 is designed to drive the inputs of an opto- coupler directly. standard i 2 c/smbus devices typically cannot drive opto-couplers, so u1 is used to buffer the signals from the host controller side. external mosfet careful selection of the power mosfet is critical to system reliability. ltc recommends either fairchild irfm120a, fdt3612, fdmc3612 or philips pht6nq10t for their proven reliability in type 1 and type 2 pse applications. non-standard applications that provide more current than the 850ma ieee maximum may require heat sinking and other mosfet design considerations. contact ltc ap - plications before using a mosfet other than one of these recommended parts. sense r the ltc4266 is designed to use either 0.5 or 0.25 current sense resistors. for new designs 0.25 is recom - mended to reduce power dissipation; the 0.5 option is intended for existing systems where the ltc4266 is used as a drop-in replacement for the ltc4258 or ltc4259a. the lower sense resistor values reduce heat dissipation. four commonly available 1 resistors (0402 or larger package size) can be used in parallel in place of a single 0.25 resistor . in order to meet the i cut and i lim accuracy required by the ieee specification, the sense resistors should have 1% tolerance or better, and no more than 200ppm/c temperature coefficient. figure 17. positive v dd boost converter 4266 f17 r54 56k c79 2200pf gnd ith/run ltc3803 v cc 2 5 v fb 1 3 ngate q15 fdc2512 q13 fmmt723 q14 fmmt723 sense 6 4 v ee c74 100f 6.3v c75 10f 16v l3 100h sumida cdrh5d28-101nc r51 4.7k 1% r53 4.7k 1% r52 3.32k 1% 3.3v at 400ma r55 806 1% r59 0.100 1%, 1w r56 47.5k 1% r57 1k d28 b1100 r58 10 r60 10 c73 10f 6.3v l4 10h sumida cdrh4d28-100nc + c77 0.22f 100v c78 0.22f 100v c76 10f 63v
ltc4266 4266fa a pplic a tions in f or ma tion 4266 f18 v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4266 v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4266 v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4266 v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4266 v dd int scl sdain sdaout ad0 ad1 ad2 ad3 dgnd agnd ltc4266 ? ? ? 0.1f 0.1f 0.1f 0.1f 0.1f + 10f 2k 2k 0.1f 0.1f 200 200 200 200 u2 u3 u1 hcpl-063l hcpl-063l v dd cpu scl sda smbalert gnd cpu u1: fairchild nc7wz17 u2, u3: agilent hcpl-063l to controller isolated 3.3v isolated gnd 0100000 0100001 0100010 0101110 0101111 i 2 c address figure 18. opto-isolating the i 2 c bus
ltc4266 4266fa output cap each port requires a 0.22f cap across its outputs to keep the ltc4266 stable while in current limit during startup or overload. common ceramic capacitors often have sig - nificant voltage coefficients; this means the capacitance is reduced as the applied voltage increases. to minimize this problem, x7r ceramic capacitors rated for at least 100v are recommended. esd/cable discharge protection ethernet ports can be subject to significant esd events when long data cables, each potentially charged to thou - sands of volts, are plugged into the low impedance of the rj45 jack. to protect against damage, each port requires a pair of clamp diodes; one to agnd and one to v ee (figure 10). an additional surge suppressor is required for each ltc4266 chip from v ee to agnd. the diodes at the ports steer harmful surges into the supply rails, where they are absorbed by the surge suppressor and the v ee bypass capacitance. the surge suppressor has the additional benefit of protecting the ltc4266 from transients on the v ee supply. s1b diodes work well as port clamp diodes, and an smaj58a or equivalent is recommended for the v ee surge suppressor. l a yout guidelines standard power layout guidelines apply to the ltc4266: place the decoupling caps for the v dd and v ee supplies near their respective supply pins, use ground planes, and use wide traces wherever there are significant currents. the main layout challenge involves the arrangement of the current sense resistors, and their connections to the ltc4266. because the sense resistor values are very low, layout parasitics can cause significant errors. care is required to achieve specified accuracy, particularly with disconnect currents. figure 19 illustrates the problem. in the example on the left, two ports have load currents i 1 and i 2 that return to the v ee power supply through a mutual resistance r m . r m represents the combined resistances of any traces, planes, and vias in the pcb that i 1 and i 2 share as they return to the v ee supply. the ltc4266 measures the volt- age difference between its sense and v ee pins to sense the voltage drop across r s1 , but as the example shows, r m introduces errors. the example on the right shows how errors can be minimized with a good layout. the circuit is rearranged so that r m no longer affects v s , and the v ee connection to the ltc4266 is used as a kelvin sense trace. v ee is not a perfect kelvin connection because all four ports con- trolled by the ltc4266 share the same sense trace, and because the current through the trace (i ee ) is not zero. however, as the equation shows, the remaining error is a small offset term. figure 20 shows two ltc4266 chips controlling eight ports (a though h). the ports are separated into two groups of four; each has its own trace on the top pcb layer that a pplic a tions in f or ma tion r m + v s + v s r s1 mutual resistance r s2 4266 f19 i ee ? ? i 1 i 2 i 1 + i 2 + i ee v s = i 1 r s1 + i 1 r m + i 2 r m ltc4266 gate sense signal scale error crosstalk error v ee r k r m r s1 kelvin sense line r s2 i ee i 1 i 2 v s = i 1 r s1 ? i ee r k i 1 + i 2 + i ee ltc4266 gate sense signal small offset error v ee figure 19. layout affects current readback accuracy
ltc4266 4266fa u1 ltc4266 ports a through d sense1 sense2 sense3 sense4 v ee via via 4266 f20 by keeping these copper fills separate on the surface, mutual resistance between ports a-d and e-h is eliminated this trace provides v ee to u1 but also acts as a kelvin sense line for ports a-d v ee copper fill on surface layer v ee plane on inner layer u2 ltc4266 ports e through h sense1 sense2 sense3 sense4 v ee r sense return to v ee power supply figure 20. layout strategy to reduce mutual resistance a pplic a tions in f or ma tion figure 21. good pcb layout example 4266 f21 port a r sense port b r sense four large vias to v ee plane pin 1 u1 the paddle is connected to v ee pins kelvin sense trace connects u1 to v ee through the vias on the right edge of v ee plane (on some inner layer) vias to source pin of the port d mosfet located on the opposite side of the board hole in v ee plane port c r sense port d r sense connects to the v ee plane with a via. currents from the u1 sub-circuit are effectively isolated from the u2 sub-circuit, reducing the layout problem down to 4-port chunks; this arrangement can be expanded for any number of ports. figure 21 shows an example of good 4-port layout. each 0.25 sense resistor consists of four 1 resistors in paral - lel. the four groups of resistors are arranged to minimize the overlap in their current flows, which minimizes mutual resistance. the horizontal slits cut in the copper help to keep the currents separate. wide copper paths connect each group of resistors to the vias at the center, so the resistance is very low. proper connection of the sense line is also important. in figure 21, u1 is not connected directly to the v ee plane but is connected instead to a kelvin sense trace that leads to the sense resistor array. similarly, the via at the center of the sense resistor array has a matching hole in the v ee plane. this arrangement prevents the mutual resistance of the four large vias from influencing the current measurements.
ltc4266 4266fa pa ck a ge description gw36 ssop 0204 0 ? 8 typ 0.355 ref 0.231 ? 0.3175 (.0091 ? .0125) 0.40 ? 1.27 (.015 ? .050) 7.417 ? 7.595** (.292 ? .299) s 45 0.254 ? 0.406 (.010 ? .016) 2.286 ? 2.388 (.090 ? .094) 0.1 ? 0.3 (.004 ? .0118) 2.44 ? 2.64 (.096 ? .104) 0.800 (.0315) bsc 0.28 ? 0.51 (.011 ? .02) typ 15.291 ? 15.545* (.602 ? .612) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 10.11 ? 10.55 (.398 ? .415) 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 10.804 min recommended solder pad layout 7.75 ? 8.258 19 36 18 1 0.800 bsc 0.520 0.0635 1.40 0.127 dimension does not include mold flash. mold flash shall not exceed 0.152mm (0.006") per side * dimension does not include interlead flash. interlead flash shall not exceed 0.254mm (0.010") per side ** millimeters (inches) note: 1. controlling dimension: millimeters 2. dimensions are in gw package 36-lead plastic ssop (wide .300 inch) (reference ltc dwg # 05-08-1642)
ltc4266 4266fa p a ck a ge d escription 5.00 p 0.10 note: 1. drawing conforms to jedec package outline m0-220 variation whkd 2. drawing not to scale 3. all dimensions are in millimeters pin 1 top mark (see note 6) 37 1 2 38 bottom view?exposed pad 5.50 ref 5.15 0.10 7.00 p 0.10 0.75 p 0.05 r = 0.125 typ r = 0.10 typ 0.25 p 0.05 (uh) qfn ref c 1107 0.50 bsc 0.200 ref 0.00 ? 0.05 recommended solder pad layout apply solder mask to areas that are not soldered 3.00 ref 3.15 0.10 0.40 p0.10 0.70 p 0.05 0.50 bsc 5.5 ref 3.00 ref 3.15 0.05 4.10 p 0.05 5.50 p 0.05 5.15 0.05 6.10 p 0.05 7.50 p 0.05 0.25 p 0.05 package outline 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 notch r = 0.30 typ or 0.35 s 45o chamfer information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. uhf package 38-lead plastic qfn (5mm 7mm) (reference ltc dwg # 05-08-1701 rev c)
ltc4266 0 4266fa r el a te d pa rts part number description comments lt3803 constant frequency current mode flyback dc/dc controller in thinsot? 200khz operation, adjustable slope compensation ltc4258 quad ieee 802.3af poe pse controller dc disconnect sensing only ltc4263 single ieee 802.3af pse controller internal fet switch ltc4263-1 high power single poe pse controller with internal fet switch ltc4265 ieee 802.3at pd interface controller 100v, 1a internal switch, 2-event classification recognition ltc4267 ieee 802.3af pd interface with integrated switching regulator internal 100v, 400ma switch, dual inrush current, programmable class ltc4268-1 high power pd with synchronous flyback controller no opto-coupler required ltc4269-1 ieee 802.3at pd interface integrated switching regulator 2-event classification, programmable classification, synchronous no-opto flyback controller, 50khz to 250khz ltc4269-2 ieee 802.3at pd interface integrated switching regulator 2-event classification, programmable classification, synchronous forward controller, 100khz to 500khz ? linear technology corporation 2009 lt 0810 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 4 34-0507 www.linear.com 4266 f22 1 2 3 4 5 6 7 8 2k 2k 1f 100v x7r 0.1 f 0.1 f 200 200 200 200 u2 u3 u1 hcpl-063l hcpl-063l v dd cpu scl sda gnd cpu interrupt d tss : diodes inc smaj58a q1: fairchild irfm120a or philips pht6nq10t u1: fairchild nc7wz17 u2, u3: agilent hcpl-063l fb1, fb2:tdk mpz2012s601a t1: pulse h6096nl or coilcraft eth1-230ld to controller phy (network physical layer chip) 0.22f 100v x7r v ee sense gate out v dd scl sdain sdaout int r s 0.25 q1 t1 1/4 ltc4266 dgnd agnd ?48v isolated smaj58a s1b isolated 3.3v isolated gnd 0.01f 200v 0.01f 200v 0.01f 200v 0.01f 200v 75 75 75 75 rj45 connector 1000pf 2000v ? ? ? ? ?? ?? ? ? ? ? fb1 fb2 s1b figure 22. one complete isolated powered etherent port t ypic a l applic a tion

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